1. Field of the Invention
The present invention relates in general to integrated circuit (IC) manufacturing, and, more specifically, to methods in IC manufacturing processes for sorting IC devices using identification (ID) codes, such as fuse ID's, in the devices.
2. State of the Art
Integrated circuits (IC's) are small electronic circuits formed on the surface of a wafer of semiconductor material, such as silicon, in an IC manufacturing process referred to as "fabrication." Once fabricated, IC's are electronically probed to evaluate a variety of their electronic characteristics, cut from the wafer on which they were formed into discrete IC dice or "chips," and then assembled for customer use using various well-known IC packaging techniques, including lead frame packaging, Chip-On-Board (COB) packaging, and flip-chip packaging.
Before being shipped to customers, packaged IC's are generally tested to ensure they will function properly once shipped. Testing typically involves a variety of known test steps, such as pre-grade, burn-in, and final, which test IC's for defects and functionality and grade IC's for speed.
As shown in FIG. 1, a variety of data are collected as IC's proceed through an IC manufacturing process. For example, fabrication deviation data reflecting quality deviations, such as fabrication process errors, are collected during fabrication and summarized in one or more reports commonly referred to as "Quality Deviation Reports" (QDR's). Similarly, data are collected during probe which record the various electronic characteristics of the IC's tested during probe.
When any of the wafers in a wafer lot are deemed to be unreliable because they are low yielding wafers, as indicated by the collected probe data, or because they are misprocessed wafers, as indicated by the QDR's, all the IC's from the wafers in the wafer lot typically undergo special testing, such as enhanced reliability testing, that is more extensive and strict than standard testing. Since a wafer lot typically consists of fifty or more wafers, many IC's that undergo the special testing do not require it because they come from wafers that are not deemed unreliable. Performing special testing on IC's that do not need it is inefficient because such testing is typically more time-consuming and uses more resources than standard testing. Therefore, there is a need in the art for a method of identifying those IC's in a wafer lot that require special testing and sorting the IC's in the wafer lot into those that require special testing and those that do not.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some methods have been devised to electronically identify individual IC's. Such methods take place "off" the manufacturing line, and involve the use of electrically retrievable identification (ID) codes, such as so-called "fuse ID's," programmed into individual IC's to identify the IC's. The programming of a fuse ID typically involves selectively blowing an arrangement of fuses and anti-fuses in an IC so that when the fuses or anti-fuses are accessed, they output a selected ID code. Unfortunately, none of these methods addresses the problem of identifying and sorting IC's "on" a manufacturing line.